The basic architecture of most data processing systems today includes a digital processor and random access memory. For economic reasons, the random access memory ("RAM") is often dynamic random access memory ("DRAM").
Typical operating frequencies for asynchronous DRAMs are in the range of 33 Mhz. For system clock rates above this range, the DRAM becomes a bottleneck that forces the processor and other components to wait for memory access. The same problem exists for more expensive memories as well, such as static random access memory ("SRAM"), electrically erasable programmable read-only memory ("EEPROM"), other programmable read-only memory ("PROM"), and read-only memory ("ROM").
Recently, synchronous dynamic random access memories ("SDRAM") have been proposed to better take advantage of inherent DRAM bandwidth. With synchronous DRAMs, data is clocked in and out of the memory device at relatively high rates. For example, synchronous DRAMs that use a pipeline architecture may be capable of running at speeds of 100 Mhz. However, the pipeline approach presents significant limitations that may prevent operation at speeds greater than 100 Mhz. With the pipeline approach, the internal access path is divided into stages, and each stage is updated with new data on every clock edge. Once the first data bit (or group of bits) is accessed, the remaining bits can be accessed every clock cycle. However, the speed of each write access is limited by the time it takes to decode column addresses. Presently, this operation takes approximately 12-15 nanoseconds, and thus the pipeline approach may not be capable of operating at speeds greater than 100 Mhz.
Moreover, high speed internal operation is often difficult and expensive in any synchronous design, because of complex timing requirements and inherent operating speed limitations of various components, such as sense amps and decoding circuitry.